The workshop will cover the following areas of interest:

• Scaling effects for sub-100nm metal structures: grain growth and microstructure
• Cu interconnect integration – Materials and reliability
• Ultra low-k dielectrics: Materials and reliability
• 3D integration, TSV and effect on stressed devices
• Advanced nanoscale materials and structures
• Synchrotron-radiation based and lab-based X-ray techniques for metal characterization
• Stress-induced degradation phenomena and failure: Cu stress, EM, SIV
• Strain/stress measurements and modeling/simulation.

Talks

last update: July 4, 2010

T1		George Pharr, University of Tennessy, US	Measurement of elastic modulus and residual stress in thin metallic films by nanoindent. and thin film bridges
T2		C. K. Hu, IBM Yorktown/NY, US	Effect of impurity on Cu electromigration
T3		Oliver Aubel, Globalfoundries, Dresden/Germany	Stress phenomena in times of porous low-k dielectrics
T4		Kaz Hirakawa, University of Tokyo/Japan	Elementary process of electromigration at metallic nanojunctions in the ballistic regime
T5		Gunther Richter, MPI Stuttgart, Germany	Synthesis of metallic nanowires
T6		Paul S. Ho, UT Austin/TX, US	Effect of cap layer and grain size on electromigration reliability of Cu/low-k interconnects for 45nm technology node
T7		Katayun Barnak, Carnegie Mellon University, US	Experimental studies on interfacial and grain boundary scattering in Cu
T8		King-Ning Tu, UCLA, US	Improved interconnect properties for nanotwinned copper: Microstrcuture and stability
T9		Chien-Neng Liao, National Tsing Hua University, Taiwan	Electromigration studies at surfaces and grain boundaries using in-situ TEM
T10		Rene Huebner, Fraunhofer IZFP, Dresden, Germany	Small grain characterization in sub-100nm Cu interconnect structures using OIM in the TEM
T11		Joost J. Vlassak, Harvard University, US	Highly stretchable metallic and ceramic films on polyimide substrates
T12		Sigurd Wagner, Princeton University, US	Making gold elsatic and silicon dioxide flexible
T13		Johan Hoefnagels, Eindhoven University of Technology, Netherlands	Copper-rubben interface delamination in stretchable electronics
T14		Junichi Koike, Tohoku University, Sendai, Japan	Cu-Mn self-forming barrier and CVD-MnOx barrier for advanced interconnect structures
T15		Paul Besser, Unity Semi/CA, US	Stress gradients in capped Cu films
T16		Juan J. Perez-Camacho, Intel, Ireland	Some challenges in strain metrology for IC manufacturing: The case of X-ray topography
T17		Michael Feser, Xradia, Concord/CA, US	X-ray tomography at on-chip and 3D interconnects: A new failure localization technique
T18		Perroud Olivier, CNRS Marseille/France	Local stress determination using m-Laue diffraction in Cu MEMS struct.
T19		Alex Dommann, CSEM Neuchatel/Switzerland	Quality control on strained semiconductor devices
T20		Reinhard Dauskardt, Stanford University, US	Mechanical properties of hybride glass films: Computational models and experiments
T21		Xiao-Hu Liu, IBM Yorktown/NY, US	Integration and reliability impact of mechanical properties of ultra low-k dielectrics beyond 32 nm technology
T22		Miroslaw Miller, TU Wroclaw, Poland	Advanced nanoporous functional layer materials with extremely low dielectric constant
T23		Minhua Lu, IBM Yorktown/NY, US	Effect of Sn grain orientation and alloy doping on the electromigration degradation mechanism for Sn-based Pb-free solders
T24		Rui Huang, UT Austin/TX, US	Thermomechanical reliability challenges for 3D interconnects
T25		Armin Klumpp, Fraunhofer IZM, Munich, Germany	Through Silicon Via technology and SLID assembly for integrated systems
T26		Geert van der Plaas, IMEC Leuven, Belgium	3D integration with Cu TSV: Technology, design and stress
T27		Valeriy Sukharev, Mentor Graphics/CA, US	Stress-induced effects caused by TSV packaging on advanced semiconductor processes
T28		Robert Geer, Nanotech Albany/NY, US	Profiling of process-induced stress in Cu TSVs for wafer-scale 3D integration
T29		K. J. Ganesh, UT Austin/TX, US	Quality control on strained semiconductor devices