stress-workshop 2010

Scope of the Workshop

The workshop will provide a forum for presenting current research and for discussions on issues related to stress-induced phenomena in on-chip metal interconnects and solder joints. Stresses arising in metal structures and surrounding dielectric materials due to novel process steps, thermal mismatch of thin film materials, electromigration or microstructure changes can lead to degradation and failure of microelectronic products.

The workshop will cover the following areas of interest:

Scaling effects for sub-100nm metal structures: grain growth and microstructure
Cu interconnect integration – Materials and reliability
Ultra low-k dielectrics: Materials and reliability
3D integration, TSV and effect on stressed devices
Advanced nanoscale materials and structures
Synchrotron-radiation based and lab-based X-ray techniques for metal characterization
Stress-induced degradation phenomena and failure: Cu stress, EM, SIV
Strain/stress measurements and modeling/simulation.

The implementation of low dielectric constant materials into the inlaid copper backend-of-line process has brought new challenges for process integration, design optimization and reliability. Understanding stress-related phenomena in new materials and structures is critical for development and integration of future metal structures in microelectronic products.

Stress-related phenomena extending beyond metal interconnects in microelectronics are also of interest, including nanostructures and thin film devices such as MEMS/NEMS.
Following the spirit of previous workshops, new research results and advances in basic understanding are emphasized.